Reconfigurable Viterbi Decoder
نویسندگان
چکیده
Forward Error Correction (FEC) schemes are an essential component of wireless communication systems. Convolutional codes are employed to implement FEC but the complexity of corresponding decoders increases exponentially according to the constraint length. Present wireless standards such as Third generation (3G) systems, GSM, 802.11A, 802.16 utilize some configuration of convolutional coding. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. The Viterbi algorithm, which is the most extensively employed decoding algorithm for convolutional codes. The main aim of this project is to design FPGA based viterbi algorithm which encrypts / decrypts the data . In this project the encryption / decryption algorithm is designed and programmed in to the FPGA.
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